This application is based upon and claims priority of Japanese Patent Application No. 2001-312410, filed on Oct. 10, 2001, the contents being incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method, more particularly to a field-effect transistor employing therein a different semiconductor junction.
2. Description of the Related Art
Taking the Si-CMOS structure, which is mainly well-known in the semiconductor integrated circuit as a typical example, the details will be explained.
The mobility differences between an electron and a hole due to the physical property of Si in itself affect performances of an n-channel transistor and a p-channel transistor, so that the improvements in the performance and the integration degree of CMOS semiconductor are disturbed.
In order to solve this problem, a device is invented wherein an n-channel film (Si film) and a p-channel film (SiGe film) are laminated by a heterojunction with a different semiconductor (SiGe) aiming at a performance improvement of the p-channel transistor (see, for example, Japanese Patent Laid-open No. Hei 3-280437).
In the MOSFET having the conventional semiconductor heterostructure taught in the document, carriers are injected via a pn-junction of a source and each channel. The carriers may be injected evenly to both channels.
The most holes injected flow at a channel formed on an interface of Si/SiGe, while a little thereof tends to flow at a channel formed on an interface of SiO2/Si. This phenomenon is called a parallel conduction.
This parallel conduction lowers the hole mobility of the p-MOSFET having the semiconductor heterostructure to thereby waste an increase merit of mobility by the Si/SiGe channel.
With a miniaturization of the MOSFET, which has the semiconductor heterostructure, difficult complexities of doping process may appear because of a creation of complicated doping profile preventing a short channel effect, and a variation of threshold voltage with a dispersion of impurities concentration.
The present invention is conceived reviewing the problems described above by providing a Schottky barrier-type source using metal and a drain for an n-channel and a p-channel laminated on the same substrate. This structure realizes that carriers can be injected selectively to each channel with restraining the short channel effect, which provides a new structure of the MOSFET having a semiconductor heterostructure. The thus-achieved selective carrier injection solves the parallel conduction issue. It is an object of the present invention to drastically upgrade the performance of the MOSFET, which has the semiconductor heterostructure.
The present invention reaches various aspects described below through a committed consideration.
A semiconductor device of the present invention includes a semiconductor substrate laminated with at least a first semiconductor film and a second semiconductor film to have a different semiconductor junction and having a channel portion therein; a gate insulation film provided on the semiconductor substrate; a gate electrode provided on the gate insulation film to be processed to a specific shape; and electrodes provided on both sides of the gate electrode and having metal or semiconductor-intermetallic compound therein.
Another aspect of the semiconductor device of the present invention includes the semiconductor substrate laminated with at least the first semiconductor film and the second semiconductor film to have the different semiconductor junction; the gate insulation film provided on the semiconductor substrate; the gate electrode provided on the gate insulation film to be processed to the specific shape; and a pair of impurity diffusion films of semiconductor-intermetallic compound provided on the surface of the semiconductor substrate in both sides of the gate electrode to feed metal reaching to the first and second semiconductor films 1, 2.
Still another aspect of the semiconductor device of the present invention includes the semiconductor substrate laminated with at least the first semiconductor film and the second semiconductor film to have the different semiconductor junction and having a channel portion therein; the gate insulation film provided on the channel portion; the gate electrode provided on the gate insulation film to be processed to a specific shape; and a pair of electrode films of the metal or the semiconductor-intermetallic compound joined on both sides of the channel portion.
Yet another aspect of the semiconductor device of the present invention is to operate with a selective carrier injection into each channel via a Schottky barrier generated in a semiconductor heterojunction of a different band gap with the metal or the semiconductor-intermetallic compound, and with an addition of modulation to the Schottky barrier through an electric field effect from the gate electrode.
A manufacturing method of the semiconductor device of the present invention includes the steps of providing on the substrate a different semiconductor lamination structure through the different semiconductor junction between the first semiconductor film and the second semiconductor film; providing the gate insulation film on the different semiconductor lamination structure; patterning the gate electrode in the specific shape on the gate insulation film; patterning a pair of metallic films in a specific shape on the different semiconductor lamination structure in both sides of the gate electrode; and providing a pair of impurity diffusion films of semiconductor-intermetallic compound by diffusing metal of the metallic films reaching to the first and second semiconductor films of the different semiconductor lamination structure.
Another aspect of the manufacturing method of the semiconductor device of the present invention includes the steps of providing on the substrate the different semiconductor lamination structure through the different semiconductor junction between the first semiconductor film and the second semiconductor film; providing the gate insulation film on the different semiconductor lamination structure; patterning the gate electrode in the specific shape on the gate insulation film; providing the channel portion by removing the different semiconductor lamination structure except for a neighborhood site under the gate electrode; and patterning the pair of electrode films of the metal or the semiconductor-intermetallic compound as joining with both sides of the channel portion.